The increasing interest in higher data rate communication applications requires high-speed and high-resolution analog-to-digital converters (ADCs). One way of achieving such ADCs is to employ a time-interleaved architecture. Time-interleaved architectures provide a benefit of increased sampling rate for an analog signal and may employ a broad spectrum of ADC technologies. However, this benefit is usually achieved at the expense of both larger semiconductor die area and power consumption.
Time-interleaved ADCs (TIADCs) also generally provide conversion-related errors due to mismatches among channel ADCs that occur in the areas of offset, gain and timing. These mismatches cause spurious components in the spectrum of the TIADC thereby generally degrading the signal-to-noise-and-distortion ratio (SNDR) of the TIADC. In particular, timing mismatch errors are a primary limiting factor and give rise to higher noise power in the overall output. Such timing mismatches have generally two different aspects. These include random sampling jitter and fixed periodic timing-skew among different channels. The use of sample-and-hold amplifiers reduces timing mismatch, but usually limits the overall throughput speed of the TIADC.
Accordingly, what is needed in the art is an enhanced way to correct timing errors inherent in the use of multiple ADCs in a time-interleaved architecture.